Nanotransistors Stamped Out

Nanoimprint lithography proves its worth, making transistors for the first time

12 November 2003—Each step along the road to making smaller and smaller circuits using photolithography requires an ever-more–arduous reworking of the manufacturing process. New light sources must be invented, new optical materials purified, new photochemicals developed. But engineers led by IEEE Fellow Stephen Chou at Princeton University in New Jersey say their way could do the job for the foreseeable future without so much as polishing a new lens.

Instead of exposing a circuit’s pattern onto a blank wafer using light, nanoimprint lithography literally stamps out the circuit. Previously used only in making simple non-electronic structures such as optical gratings, the technique, as Chou and his colleague Wei Zhang have shown, can make electronics by nanoimprinting multiple transistors with features two-thirds the size of those found on even the most advanced commercial chips.

Nanoimprinting first requires etching the pattern for a circuit into a silicon wafer by conventional means. A liquefied polymer is spread on a separate silicon wafer, and the etched wafer is pressed onto it. The pressing embosses the circuit pattern into the polymer, which is set into a solid by cooling. Then a round of etching with ions transfers the embossing into the silicon.

Nanoimprinting has transferred patterns with features as small as 5 nm. Also among the technique’s advantages is that the stamp can be reused repeatedly. So even if its finest features are made using an expensive process like electron-beam lithography, the cost can be spread over hundreds of wafers, making the overall process cheap. Nanoimprint is also much faster than such nanolithography technologies as e-beam, taking as little as 60 seconds to emboss a wafer.

Using four successive stamp and etch cycles—two more than have ever been successfully applied— Zhang and Chou first showed that working MOSFET transistors could be constructed by building 1200 of the devices on a 100-mm wafer. These initial transistors had fairly coarse features by chip-making standards, the smallest of which was 1 µm. But, the experiment did show that a whole wafer of working transistors could be constructed using the technique.

Next, the Princeton engineers shrunk down their design so that the smallest part of the transistor, the length of the gate, was just 60 nm. The most advanced commercial photolithography tools make transistors with 90-nm gates. Zhang made only 20 of these 60-nm devices, but those he measured worked well. He and Chou published their work in the 25 August issue of Applied Physics Letters .

According to Zhang, the most pressing concern when using nanoimprint lithography (NIL) to make devices, especially ones with multiple layers like his transistors, is that each embossing line up as perfectly as possible with the one below it. The imprints had accuracy of 500 nm, meaning that on average they were misaligned in one direction or another by that amount.

"It can be better than that," Zhang claims. The accuracy was limited by the resolution of the microscope used to align the wafers and the landmarks on the wafer that the aligner was looking for. The landmarks he used in the experiment give only a resolution of 250 –nm, but there are other types of landmarks that are more accurate. And the Princeton pair will need those for their next experiment—complete working circuits. "That has a higher requirement of uniformity and control," says Zhang.

Although no semiconductor firms make their commercial electronics using nanoimprinting, several have nanoimprinting tools in their research laboratories, and a number of firms sell the tools, including Molecular Imprints, EV Group, Obducat, and Chou’s company, Nanonex. Another Chou-affiliated firm, NanoOpto (Somerset, N.J.), uses NIL to make optical components, such as those in the read assemblies of CD and DVD players.

Advertisement
Advertisement