Chip for Future Eye Implants Runs on Picowatts, Thanks to New Deep-Sleep Tech
Chip could run for a year on millimeter-sized battery
16 June 2008--A new microchip design uses about a 30 000th as much power as comparable chips and could lead to long-lasting implantable biosensors, researchers report this week at the VLSI Symposia, in Hawaii.
The Phoenix processor has an average power consumption of only 39 picowatts for a typical sensor application, such as monitoring pressure. That's about four orders of magnitude more efficient than other designs. The chip and sensor, enclosed in a 1-cubic-millimeter package with a thin-film battery, could run for a year or more, say David Blaauw and Dennis Sylvester, two professors of electrical engineering and computer science at the University of Michigan. Such tiny low-power processors will be useful as controllers for sensors. The chip was developed as part of a project to design a pressure sensor to be implanted in the eyes of glaucoma patients.
”There's a very big upswing of new applications [for sensors] that people are interested in if we can get the size down,” Blaauw says. ”In order to have any kind of lifetime on a small battery, you need small power.”
The Michigan team ”has an enlightened, rather unconventional view of how to reduce total energy in the sensor processor while meeting spec,” says Kerry Bernstein, a senior technical staff member in IBM's research division at Yorktown Heights, N.Y., who has worked with them in the past.
To achieve low-power operation, the team actually focused on nonoperation--the idle time that makes up more than 99 percent of the device's lifetime. In sleep mode, power gates, which are transistors that act as simple switches, block electrical current from running. In standard designs, those gates are wide to provide lower resistance when the device is turned on. But the low resistance means that even with the gate closed, a fair amount of current leaks through, wasting power. To reduce the leakage, the team went back to an older design generation. Today's chips have 45-nanometer features. The Michigan team went back four generations to the 180-nm node, creating longer, more-resistive gates. At the same time, they made them narrower, which also raises resistance. The downside is that when the device is actually running, it requires an extra 100 millivolts to overcome the gate's added resistance. But because the chip is active for only a small fraction of the time--a few hundred milliseconds every 10 minutes--overall power use is still reduced.
”We sacrificed some energy efficiency and performance when the chip is active, but because of that we can really squeeze it off when it's in sleep mode,” Blaauw says.
At the same time, they lowered the supply voltage. Most such devices operate at 1.2 volts, but the team found that the chip worked best at 400 mV. With a 400 mV supply, switching from 0 to 1 in a binary system means bringing a wire from 0 V to 0.4 V, which requires one-ninth the energy it takes to go to 1.2 V. (Blaauw has experimented with lower voltages for other, more-complicated processors. See ”Intel and ARM Are Exploring Self-Correction Schemes to Boost Processor Performance and Cut Power.”)
A lower voltage means the chip must run slower, but for sensor operations, the chip only needs to perform a few thousand instructions, so even operating at 100 kilohertz--slow compared with the chip in your laptop--it can do all it needs to in a matter of milliseconds.
Between the slower operation and the bulkier transistors, the Phoenix doesn't have the computing power of today's most-advanced chips. But for what it's designed to do, it doesn't need it. ”You have to think of performance in an Intel chip,” says Sylvester. ”In these chips, that's actually the wrong way around.”
Phoenix makes use of some other power-saving tricks. It uses a very slow timer to tell the chip when to switch back on and take a new sensor reading. Phoenix's timer operates at a frequency of less than one oscillation per second, drawing just 2 pW. The researchers also developed techniques for streamlining the set of instructions the processor must be able to execute and for compressing data in the chip's memory. With fewer instructions and less data to store, the chip requires less memory, and because the volatile memory embedded in microprocessors always requires power to retain its contents, keeping the total amount of memory down is important.
Researchers at the University of Michigan's Kellogg Eye Center want to try implanting the chip in eyes (starting, of course, with animals) to take pressure readings in patients with glaucoma, a leading cause of blindness. Knowing how pressure varies over the course of a day could help doctors tailor drug treatments for the disease.
Blaauw says the chip isn't quite ready for such tests. Although they've built a 1-square-millimeter test chip containing the processor, sensor, memory, and timer, they have yet to integrate the battery. And then they'll need to add wireless communication equipment, which may be problematic because the antennas used in standard radio-frequency identification tags, for instance, are too big to be practical.
About the Author
Neil Savage writes about lasers, LEDs, optoelectronics, and other technology from Lowell, Mass. In February 2008 he reported on another low-power processor scheme.